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The AD8015 maintains 26.5 nA referred to input (RTI) to 100
MHz. Calculations below translate this specification into minimum
power level and bit error rate specifications for SONET
and FDDI systems. The dominant sources of noise are: 10 kW
feedback resistor current noise, input bipolar transistor base
current noise, and input voltage noise.
The AD8015 has dielectrically isolated devices and bond pads
that minimize stray capacitance at the IIN pin. Input voltage
noise is negligible at lower frequencies, but can become the
dominant noise source at high frequencies due to IIN pin stray
capacitance. Minimizing the stray capacitance at the IIN pin is
critical to maintaining low noise levels at high frequencies. The
pins surrounding the IIN pin (Pins 1 and 3) have no internal
connection and should be left unconnected in an application.
This minimizes IIN pin package capacitance. [b]It is best to have no
ground plane or metal runs near Pins 1, 2, and 3 and to minimize
capacitance at the IIN pin. [/b]
The AD8015AR (8-pin SOIC) IIN pin total stray capacitance is
0.4 pF without the photodiode. Photodiodes used for SONET
or FDDI systems typically add 0.3 pF, resulting in roughly
0.7 pF total stray capacitance.
E-mail: 
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