[an error occurred while processing this directive]
|
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder is
port (
ADDR: in STD_LOGIC_VECTOR (2 downto 0);
ALE,CS_PLD: in STD_LOGIC;
SOC_CS, CLK_CS, OE_CS, DIV_MCLK_CS, DIV_CS : out STD_LOGIC
);
end;
architecture beh of decoder is
signal xCS: std_logic_vector(4 downto 0);
begin
process(ALE, ADDR)
begin
if (ALE = '0') then
xCS <= "11111";
else
case ADDR is
when "001" => xCS <= "11110";
when "010" => xCS <= "11101";
when "011" => xCS <= "11011";
when "100" => xCS <= "10111";
when "101" => xCS <= "01111";
when others => xCS <= "11111";
end case;
end if;
end process;
-- не понимаю страсти все загонять в процесс,
-- тем более в один
SOC_CS <= CS_PLD or xCS(0);
CLK_CS <= CS_PLD or xCS(1);
OE_CS <= CS_PLD or xCS(2);
DIV_MCLK_CS <= CS_PLD or xCS(3);
DIV_CS <= CS_PLD or xCS(4);
end;
E-mail: info@telesys.ru