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library IEEE;
use IEEE.std_logic_1164.all;
entity decoder is
port (
ADDR: in STD_LOGIC_VECTOR (2 downto 0);
ALE,CS_PLD: in STD_LOGIC;
SOC_CS, CLK_CS, OE_CS, DIV_MCLK_CS, DIV_CS : out STD_LOGIC
);
end;
architecture beh of decoder is
begin
process(ALE, CS_PLD, ADDR)
begin
if ((CS_PLD = '0') and (ALE = '0')) then
case ADDR is
when "001" => (DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("11110");
when "010" => (DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("11101");
when "011" => (DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("11011");
when "100" => (DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("10111");
when "101" => (DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("01111");
when others => (DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("11111");
end case;
else
(DIV_CS, DIV_MCLK_CS, OE_CS, CLK_CS, SOC_CS) <= std_logic_vector'("11111");
end if;
end process;
end;
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