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library IEEE;
use IEEE.std_logic_1164.all;
entity decoder is
port (
ADDR: in STD_LOGIC_VECTOR (2 downto 0);
ALE,CS_PLD: in STD_LOGIC;
SOC_CS, CLK_CS, OE_CS, DIV_MCLK_CS, DIV_CS : out STD_LOGIC
);
end;
architecture beh of decoder is
signal xCS: std_logic_vector(4 downto 0);
begin
SOC_CS <= xCS(0);
CLK_CS <= xCS(1);
OE_CS <= xCS(2);
DIV_MCLK_CS <= xCS(3);
DIV_CS <= xCS(4);
process(ALE,CS_PLD,xCS,ADDR)
begin
if(CS_PLD = '0' and ALE = '0') then
case ADDR is
when "001" => xCS <= "11110";
when "010" => xCS <= "11101";
when "011" => xCS <= "11011";
when "100" => xCS <= "10111";
when "101" => xCS <= "01111";
when others => xCS <= "11111";
end case;
else xCS <= "11111";
end if;
end process;
end;
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