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там довольно большой документ, это только цитата. Файл B_Design_Considerationsrev6.pdf взят с диска, где найти на сайте - точно не подскажу.
А Атмел... Ну что Вам сказать... Не люблю я эту фирму, хоть и приходится иногда использовать их продукцию
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Typically, HSCMOS devices do not latch up with currents
of 75 mA forced into or out of the inputs or 300 mA for the
outputs under worst case conditions (TA = 125C and VCC =
6 V). Under dc conditions for the inputs, the input protection
network typically fails, due to grossly exceeding the maximum
input voltage rating of – 1.5 to VCC + 1.5 V before latch–
up currents are reached. For most designs, latch up will not
be a problem, but the designer should be aware of it, what
causes it, and how it can be prevented.
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2. Ensure that inputs and outputs are limited to the maximum
rated values.
– 1.5 Vin VCC +1.5 V referenced to GND or
– 0.5 Vin VCC +0.5 V referenced to GND
– 0.5 Vout VCC +0.5 V referenced to GND
|Iin| 20 mA
|Iout| 25 mA for standard outputs
|Iout| 35 mA for bus–driver outputs
3. If voltage transients of sufficient energy to latch up the
device are expected on the inputs or outputs, external
protection diodes can be used to clamp the voltage.
Another method of protection is to use a series resistor
to limit the expected worst case current to the maximum
ratings value. See Handling Precautions for other
possible protection circuits and a discussion of ESD
prevention.
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