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Each of the dedicated global clock pins in EP20K300E, EP20K400E, EP20K600E, EP20K1000E, and EP20K1500E
devices (CLK1p,CLK2p,CLK3p,CLK4p) supplies the clock to a PLL. Each altclklock instance represents a
single PLL instantiation. All altclklock clock outputs are 50/50 duty cycle. The other general APEX 20KE usage
guidelines for altclklock
are:
1. It can only be fed directly by a dedicated clock input pin without inversion.
2. It can only be used to clock positive or negative edge-triggered registers in logic elements (LEs), input/output
elements (IOEs), or embedded system blocks (ESBs).
3. The allowable frequency input range is 1.5 to 160 MHz.
4. The allowable frequency output range on clock0 is 1.5 to 200 MHz.
5. The allowable frequency output range on clock1 is 20 to 200 MHz...........
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