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Коллеги помогите найти ошибку (vhd line 121: Signal wr_ctrl cannot be synthesized, bad synchronous description). В коде:
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dout: process (write_clock, CLK_S)
begin
if(write_clock'EVENT AND write_clock ='1' AND CLK_S'EVENT AND CLK_S='1' AND read_addr<=XBUS(2 downto 0)) then
wr_ctrl <= '1';
elsif(write_clock'EVENT AND write_clock ='1' AND CLK_S'EVENT AND CLK_S='1' AND xd_l<=XBUS(7 downto 0))
then wr_ctrl <= '0';
end if;
end process dout;
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