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проблема в следующем:
после компиляции не запускается симуляция в ModelSim 6.0
Цитата из мана:
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1. User should replace include parameter file name in ddr1_test_tb.v file with parameter file name from
RTL folder when the design is generated from the tool before the the simulations are run.
2. User should replace module name in the component instantiation part in the file ddr1_test_tb.v file with
the module name of their design.
3. After the rtl is generated, create the Model sim project file. Add all the rtl files from the rtl folder
to the project Also add the memory model, test bench and glbl files from the sim folder.
4. Compile the design.
5. After successful compilation of design load the design using the following comamnd.
vsim -t ps +notimingchecks -L ../Modeltech_6.1a/unisims_ver work.ddr1_test_tb glbl
Note : User should set proper path for unisim verilog libraries
6. After the design is successfully loaded, run the simulations and view the waveforms.
-------------------------------
все собрал в единый проект как написано и откомпилировал
но комманда vsim (естественно, с моими путями к библиотекам, с которыми тоже всё в порядке) не проходит и ругается
выдает такие вот ошибки:
# vsim +notimingchecks -L C:/Modeltech_6.0/verilog_src/unisims/work -t ps work.ddr1_test_tb glbl
# Loading work.ddr1_test_tb
# Loading work.ddr
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'reset_in' not found in the connected module (1st connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'SYS_CLK' not found in the connected module (2nd connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'SYS_CLKb' not found in the connected module (3rd connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_rst_dqs_div_in' not found in the connected module (4th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_rst_dqs_div_out' not found in the connected module (5th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_CAS_N' not found in the connected module (6th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_CKE' not found in the connected module (7th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_led_error_output1' not found in the connected module (8th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_CK' not found in the connected module (9th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_CK_N' not found in the connected module (10th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_CS_N' not found in the connected module (11th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_RAS_N' not found in the connected module (12th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_WE_N' not found in the connected module (13th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_A' not found in the connected module (14th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_DQS' not found in the connected module (15th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_BA' not found in the connected module (16th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_DM' not found in the connected module (17th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Error: (vsim-3389) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Port 'cntrl0_DDR_DQ' not found in the connected module (18th connection).
# Region: /ddr1_test_tb/mem_interface_top
# ** Fatal: (vsim-3365) C:/Temp/nnnnnnn/ddr1_test_tb.v(103): Too many port connections. Expected 12, found 18.
# Time: 0 ps Iteration: 0 Instance: /ddr1_test_tb/mem_interface_top File: C:/Temp/nnnnnnn/mem_interface_top/sim/ddr.v
# FATAL ERROR while loading design
# Error loading design
-------------------------------------
прилагаю файл на который ругается
---------------ddr1_test_tb.v--------
`include "mem_interface_top_parameters_0.v"
`timescale 1ps / 1ps
module ddr1_test_tb;
parameter CLOCK_PERIOD = 5000;
parameter HALF_CLK_PERIOD = 2500;
reg clk ;
wire clkb ;
reg rst ;
wire [`clk_width-1:0] ddr_clk;
wire [`clk_width-1:0] ddr_clkb;
wire [`data_strobe_width-1:0] ddr_dqs_fpga ;
wire [`data_strobe_width-1:0] ddr_dqs_sdram ;
wire [`data_width-1:0] ddr_dq_fpga ;
wire [`data_width-1:0] ddr_dq_sdram ;
wire ddr_cke ;
wire ddr_csb ;
wire ddr_rasb ;
wire ddr_casb ;
wire ddr_web ;
wire [`data_mask_width-1:0] ddr_dm;
wire [1:0] ddr_ba ;
wire [`row_address-1:0] ddr_address ;
wire [2:0]CMD ;
reg enable_o ;
reg enable ;
wire led_error_output1 ;
wire rst_dqs_div ;
wire rst_dqs_div1;
wire gnd ;
wire tmp ;
wire tmp1 ;
wire [(2*`data_width)-1:0] read_data_out ;
wire [(2*`data_width)-1:0] lfsr_data_out ;
assign CMD = {ddr_rasb, ddr_casb , ddr_web};
assign dip1 = 1'b1;
assign dip2 = 1'b1;
assign clkb = ~ clk;
assign gnd = 1'b0;
assign #4000 rst_dqs_div1 = rst_dqs_div;
always @(posedge clk)
begin
if (!rst)
begin
enable_o <= 1'b0;
enable <= 1'b0;
end
else if(CMD == 3'b100) // write
enable_o <= 1'b0;
else if(CMD == 3'b101) // read
enable_o <= 1'b1;
else
enable_o <= enable_o;
enable <= enable_o;
end
// During a READ
assign #100 ddr_dqs_fpga = (enable) ? ddr_dqs_sdram : 8'bz;
assign #100 ddr_dq_fpga = (enable) ? ddr_dq_sdram : 64'bz;
// During a WRITE
assign #50 ddr_dqs_sdram = (!enable_o) ? ddr_dqs_fpga : 8'bz;
assign ddr_dq_sdram = (!enable_o) ? ddr_dq_fpga : 64'bz;
//Clock Generation
initial clk <= 1'b0;
always #3750 clk <= ~clk;
// RESET Generation
initial
begin
rst <= 1'b0;
#25000 rst <= 1'b1;
end
ddr mem_interface_top (
.reset_in (rst),
.SYS_CLK (clk),
.SYS_CLKb (clkb),
.cntrl0_rst_dqs_div_in (rst_dqs_div),
.cntrl0_rst_dqs_div_out (rst_dqs_div),
.cntrl0_DDR_CAS_N (ddr_casb),
.cntrl0_DDR_CKE (ddr_cke),
.cntrl0_led_error_output1 (led_error_output1),
.cntrl0_DDR_CK (ddr_clk),
.cntrl0_DDR_CK_N (ddr_clkb),
.cntrl0_DDR_CS_N (ddr_csb),
.cntrl0_DDR_RAS_N (ddr_rasb),
.cntrl0_DDR_WE_N (ddr_web),
.cntrl0_DDR_A (ddr_address),
.cntrl0_DDR_DQS (ddr_dqs_fpga),
.cntrl0_DDR_BA (ddr_ba),
.cntrl0_DDR_DM (ddr_dm),
.cntrl0_DDR_DQ (ddr_dq_fpga)
);
ddr mt46v16m16_0 (
.Dq ( ddr_dq_sdram),
.Dqs ( ddr_dqs_sdram),
.Addr ( ddr_address),
.Ba ( ddr_ba),
.Clk ( ddr_clk),
.Clk_n ( ddr_clkb),
.Cke ( ddr_cke),
.Cs_n ( ddr_csb),
.Ras_n ( ddr_rasb),
.Cas_n ( ddr_casb),
.We_n ( ddr_web),
.Dm ( ddr_dm)
);
endmodule
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как решиь проблему ?
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