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Компильните,плз,Квартусом следующее(тест):
library IEEE;
use IEEE.STD_LOGIC_1164.all;ENTITY proba IS
PORT
(
clk1 : IN STD_LOGIC;
outs : out STD_LOGIC
);
END proba;ARCHITECTURE rtl OF proba IS
type T_state is (s0,s1);
signal State : T_state := s0;
BEGIN
process (clk1,state)begin
case state is
when s0 =>
if (RISING_EDGE(clk1)) then
State <= s1;
outs <= '1';
end if;
when s1 =>
if (RISING_EDGE(clk1)) then
State <= s0;
outs <= '0';
end if;
end case;
end process;END rtl;
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