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Reliability Implications of Permanently Enabling 5V SRAMs
Introduction
Leaving 5V-unregulated Fast Asynchronous SRAMs in a
powered-on (enabled) idle state for long periods of time can
cause permanent damage to the part. This application note
provides a description of the problem and suggests means of
correction.
Problem Description
The problem arises in customer applications which keep the
SRAM in a powered-on idle state for a long period of time,
with address bits that go unchanged. Failures are observed
at bits corresponding to the addressed row within the SRAM.
Failures have only been observed in applications with system
voltages of at least 5V. All applications had grounded chip-enable
(CE), permanently enabling the SRAM.
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The diagram above illustrates the basic problem. If the SRAM
is enabled, then a certain group of SRAM cells will be conducting
current through the bitlines (BL or BLB, depending on
the data present in the cell). If the device is held in this condition,
typically a year or longer, the constant current flow can
gradually degrade the transistors to the point of failure. The
minimum duration over which this degradation occurs depends
strongly on the applied voltage and transistor dimensions.
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