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module dff1 (q, d, clk, load, data);
input d, clk, load, data;
output q;
wire tmp_set = load & data;
wire tmp_rst = load & ~data;
reg q;
always @(posedge clk or posedge tmp_set or posedge tmp_rst )
begin
if (tmp_rst)
q <= 0;
else if (tmp_set)
q <= 1;
else
q <= d;
end
endmodule
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