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begin -- RTL
-- purpose: SHIFT REGISTER TO IMPLEMENT MATCH FILTER DELAY
-- type : sequential
srl_proc: process (clk)
begin -- process SRL
if clk'event and clk = '1' then -- rising clock edge
for i in 1 to cfg_word.DELAY-1 loop
tmp(i+1)<=tmp(i);
end loop; -- i
tmp(1)<=in_stream;
end if;
end process SRL_proc;
adder: if cfg_word.COFF = 1 generate
summ<=sxt(tmp(cfg_word.DELAY),summ'length)+sxt(in_sample,summ'length);
end generate adder;
subser: if cfg_word.COFF = -1 generate
summ<=sxt(tmp(cfg_word.DELAY),summ'length)-sxt(in_sample,summ'length);
end generate subser;
-- purpose: LATCH STAGE OUTPUT VALUE
-- type : sequential
out_latch: process (clk)
begin -- process out_latch
if clk'event and clk = '1' then -- rising clock edge
summ_ff<=summ;
end if;
end process out_latch;
out_stream<=summ_ff;
end RTL;
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