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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div16 is
port (
CLK : in std_logic;
RESET : in std_logic;
CLK_d16 : out std_logic
);
end div16;
architecture behav of div16 is
signal COUNT_VALUE : std_logic_vector(3 downto 0);
begin
process (CLK, RESET)
begin
if RESET = '1' then
COUNT_VALUE <= "0000";
elsif rising_edge(CLK) then
COUNT_VALUE <= COUNT_VALUE +1;
end if;
end process;
CLK_d16 <= COUNT_VALUE(3);
end behav;
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