module test_make (Reset, nCs, nWr_Rd, DataBidir, DataIn, DataOut);

// Global
input Reset;
// Bus
input nCs;
input nWr_Rd;
inout [7:0] DataBidir; wire [7:0] DataBidir;
// user data
input [7:0] DataIn;
output [7:0] DataOut; reg [7:0] DataOut;


wire ReadEna, WriteEna;
assign ReadEna=nWr_Rd;
assign WriteEna=!nWr_Rd;

always @(posedge nCs or negedge Reset)
if (!Reset) begin
DataOut=8'd0;
end //if
else begin
if (WriteEna)
DataOut=DataBidir;
end //else

// можно упростить
assign DataBidir=(nCs)?8'bzzzzzzzz:( (ReadEna)?DataIn:8'bzzzzzzzz );

endmodule //test_make