Например, старшие разряды шины адреса -> col, младшие -> row ?
(С учетом применения core with:)
SDRAM chips are arranged as multiple banks of memory with each bank capable of independent open row address management. This controller takes advantage of open row management for a single bank. Systems or applications that frequently change the destination bank for operations will require extra management cycles (row closings and openings) to access data. Continuous reads or writes within the same row and bank will operate at rates approaching one word per clock.