 Разработка, производство и продажа радиоэлектронной аппаратуры  |
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DDR = C:\Modeltech_6.3c\xilinx\DDR
------------------------------------------------------------------------------
-- system_tb.vhd
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE STD.textio.all;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
USE IEEE.STD_LOGIC_TEXTIO.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_tb is
end system_tb;
architecture STRUCTURE of system_tb is
Component HY5DU281622AT
Generic (
TimingCheckFlag : boolean := FALSE; -- If FALSE, all the timing violations won't be checked.
PUSCheckFlag : boolean := FALSE -- If not using power-up sequence, it's value must be FALSE.
-- Part_Number : PART_NUM_TYPE := K -- Speed Bin. (There are 3 kinds of speed bins, K, H and L.)
);
Port ( VDD1 : in std_logic;
DQ0 : inout std_logic := 'Z';
VDDQ3 : in std_logic;
DQ1 : inout std_logic := 'Z';
DQ2 : inout std_logic := 'Z';
VSSQ6 : in std_logic;
DQ3 : inout std_logic := 'Z';
DQ4 : inout std_logic := 'Z';
VDDQ9 : in std_logic;
DQ5 : inout std_logic := 'Z';
DQ6 : inout std_logic := 'Z';
VSSQ12 : in std_logic;
DQ7 : inout std_logic := 'Z';
NC14 : in std_logic;
VDDQ15 : in std_logic;
LDQS : inout std_logic := 'Z';
NC17 : in std_logic;
VDD18 : in std_logic;
NC19 : in std_logic;
LDM : in std_logic;
WEB : in std_logic;
CASB : in std_logic;
RASB : in std_logic;
CSB : in std_logic;
NC25 : in std_logic;
BA0 : in std_logic;
BA1 : in std_logic;
A10 : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
VDD33 : in std_logic;
VSS34 : in std_logic;
A4 : in std_logic;
A5 : in std_logic;
A6 : in std_logic;
A7 : in std_logic;
A8 : in std_logic;
A9 : in std_logic;
A11 : in std_logic;
NC42 : in std_logic;
NC43 : in std_logic;
CKE : in std_logic;
CLK : in std_logic;
CLKB : in std_logic;
UDM : in std_logic;
VSS48 : in std_logic;
VREF : in std_logic;
NC50 : in std_logic;
UDQS : inout std_logic := 'Z';
VSSQ52 : in std_logic;
NC53 : in std_logic;
DQ8 : inout std_logic := 'Z';
VDDQ55 : in std_logic;
DQ9 : inout std_logic := 'Z';
DQ10 : inout std_logic := 'Z';
VSSQ58 : in std_logic;
DQ11 : inout std_logic := 'Z';
DQ12 : inout std_logic := 'Z';
VDDQ61 : in std_logic;
DQ13 : inout std_logic := 'Z';
DQ14 : inout std_logic := 'Z';
VSSQ64 : in std_logic;
DQ15 : inout std_logic := 'Z';
VSS66 : in std_logic
);
End Component;
----------------------------------------------------------------------
-- Internal signals
signal CONTR_IN1 : std_logic;
signal CONTR_IN2 : std_logic;
signal CONTR_OUT1 : std_logic;
signal CONTR_OUT2 : std_logic;
signal DAC_MOD_SPI_CNT_1 : std_logic;
signal DAC_MOD_SPI_CNT_2 : std_logic;
signal DAC_SYN_SPI_CNT_1 : std_logic;
signal DAC_SYN_SPI_CNT_2 : std_logic;
signal DATA_OR_INIT_SIGNAL_OUT_1 : std_logic;
signal DATA_OR_INIT_SIGNAL_OUT_2 : std_logic;
signal DDR_Addr : std_logic_vector(0 to 12);
signal DDR_BankAddr : std_logic_vector(0 to 1);
signal DDR_CASn : std_logic;
signal DDR_CKE : std_logic;
signal DDR_CLK_FB : std_logic;
signal DDR_CSn : std_logic;
signal DDR_Clk : std_logic;
signal DDR_Clkn : std_logic;
signal DDR_DM : std_logic_vector(0 to 3);
signal DDR_DQ : std_logic_vector(0 to 31);
signal DDR_DQS : std_logic_vector(0 to 3);
signal DDR_RASn : std_logic;
signal DDR_WEn : std_logic;
signal EXT_CLK : std_logic;
signal EXT_TAKT : std_logic;
signal Eth1_PHY_Mii_clk : std_logic;
signal Eth1_PHY_Mii_data : std_logic;
signal Eth1_PHY_col : std_logic;
signal Eth1_PHY_crs : std_logic;
signal Eth1_PHY_dv : std_logic;
signal Eth1_PHY_rst_n : std_logic;
signal Eth1_PHY_rx_clk : std_logic;
signal Eth1_PHY_rx_data : std_logic_vector(3 downto 0);
signal Eth1_PHY_rx_er : std_logic;
signal Eth1_PHY_tx_clk : std_logic;
signal Eth1_PHY_tx_data : std_logic_vector(3 downto 0);
signal Eth1_PHY_tx_en : std_logic;
signal Eth1_PHY_tx_er : std_logic;
signal Eth2_PHY_Mii_clk : std_logic;
signal Eth2_PHY_Mii_data : std_logic;
signal Eth2_PHY_col : std_logic;
signal Eth2_PHY_crs : std_logic;
signal Eth2_PHY_dv : std_logic;
signal Eth2_PHY_rst_n : std_logic;
signal Eth2_PHY_rx_clk : std_logic;
signal Eth2_PHY_rx_data : std_logic_vector(3 downto 0);
signal Eth2_PHY_rx_er : std_logic;
signal Eth2_PHY_tx_clk : std_logic;
signal Eth2_PHY_tx_data : std_logic_vector(3 downto 0);
signal Eth2_PHY_tx_en : std_logic;
signal Eth2_PHY_tx_er : std_logic;
signal Flash_A : std_logic_vector(0 to 31);
signal Flash_CEN : std_logic_vector(0 to 3);
signal Flash_DQ : std_logic_vector(0 to 15);
signal Flash_OEN : std_logic;
signal Flash_Rst : std_logic;
signal Flash_WEN : std_logic;
signal LVPECLK_n : std_logic := '0';
signal LVPECLK_p : std_logic := '0';
signal OSH_RED : std_logic;
signal PMC_IO_1 : std_logic_vector(53 downto 0);
signal PMC_IO_1_INOUT : std_logic_vector(55 downto 54);
signal PMC_IO_2 : std_logic_vector(53 downto 0);
signal PMC_IO_2_INOUT : std_logic_vector(55 downto 54);
signal RESERV : std_logic;
signal RESET_FPGA : std_logic;
signal RS232_1_RX : std_logic;
signal RS232_1_TX : std_logic;
signal RS232_2_RX : std_logic;
signal RS232_2_TX : std_logic;
signal SIGNAL_OUT_ENABLE_1 : std_logic;
signal SIGNAL_OUT_ENABLE_2 : std_logic;
signal SI_GREEN : std_logic;
signal TC_GREEN : std_logic;
signal TEST_ON : std_logic;
signal UPR_OTKL : std_logic;
signal ZBT1_CE : std_logic;
signal ZBT1_CKE : std_logic;
signal ZBT1_CLK : std_logic;
signal ZBT1_DQ : std_logic_vector(31 downto 0);
signal ZBT1_SA : std_logic_vector(18 downto 0);
signal ZBT1_WR : std_logic;
signal ZBT2_CE : std_logic;
signal ZBT2_CKE : std_logic;
signal ZBT2_CLK : std_logic;
signal ZBT2_DQ : std_logic_vector(31 downto 0);
signal ZBT2_SA : std_logic_vector(18 downto 0);
signal ZBT2_WR : std_logic;
begin
DDR_1_inst: HY5DU281622AT
-- Generic map(
-- TimingCheckFlag => TimingCheckFlag , -- If FALSE, all the timing violations won't be checked.
-- PUSCheckFlag => PUSCheckFlag -- If not using power-up sequence, it's value must be FALSE.
-- Part_Number : PART_NUM_TYPE := K -- Speed Bin. (There are 3 kinds of speed bins, K, H and L.)
-- );
port map (
VDD1 => '1',
DQ0 => DDR_DQ(0),
VDDQ3 => '1',
DQ1 => DDR_DQ(1),
DQ2 => DDR_DQ(2),
VSSQ6 => '0',
DQ3 => DDR_DQ(3),
DQ4 => DDR_DQ(4),
VDDQ9 => '1',
DQ5 => DDR_DQ(5),
DQ6 => DDR_DQ(6),
VSSQ12 => '0',
DQ7 => DDR_DQ(7),
NC14 => '1',
VDDQ15 => '1',
LDQS => DDR_DQS(0),
NC17 => '1',
VDD18 => '1',
NC19 => '1',
LDM => DDR_DM(0),
WEB => DDR_WEn,
CASB => DDR_CASn,
RASB => DDR_RASn,
CSB => DDR_CSn,
NC25 => '1',
BA0 => DDR_BankAddr(0),
BA1 => DDR_BankAddr(1),
A10 => DDR_Addr(10),
A0 => DDR_Addr(0),
A1 => DDR_Addr(1),
A2 => DDR_Addr(2),
A3 => DDR_Addr(3),
VDD33 => '1',
VSS34 => '0',
A4 => DDR_Addr(4),
A5 => DDR_Addr(5),
A6 => DDR_Addr(6),
A7 => DDR_Addr(7),
A8 => DDR_Addr(8),
A9 => DDR_Addr(9),
A11 => DDR_Addr(11),
NC42 => '1',
NC43 => '1',
CKE => DDR_CKE,
CLK => DDR_Clk,
CLKB => DDR_CLKn,
UDM => DDR_DM(1),
VSS48 => '0',
VREF => '1',
NC50 => '1',
UDQS => DDR_DQS(1),
VSSQ52 => '0',
NC53 => '1',
DQ8 => DDR_DQ(8),
VDDQ55 => '1',
DQ9 => DDR_DQ(9),
DQ10 => DDR_DQ(10),
VSSQ58 => '0',
DQ11 => DDR_DQ(11),
DQ12 => DDR_DQ(12),
VDDQ61 => '1',
DQ13 => DDR_DQ(13),
DQ14 => DDR_DQ(14),
VSSQ64 => '0',
DQ15 => DDR_DQ(15),
VSS66 => '0'
);
DDR_2_inst: HY5DU281622AT
-- Generic map(
-- TimingCheckFlag => TimingCheckFlag , -- If FALSE, all the timing violations won't be checked.
-- PUSCheckFlag => PUSCheckFlag -- If not using power-up sequence, it's value must be FALSE.
-- Part_Number : PART_NUM_TYPE := K -- Speed Bin. (There are 3 kinds of speed bins, K, H and L.)
-- );
port map (
VDD1 => '1',
DQ0 => DDR_DQ(16),
VDDQ3 => '1',
DQ1 => DDR_DQ(17),
DQ2 => DDR_DQ(18),
VSSQ6 => '0',
DQ3 => DDR_DQ(19),
DQ4 => DDR_DQ(20),
VDDQ9 => '1',
DQ5 => DDR_DQ(21),
DQ6 => DDR_DQ(22),
VSSQ12 => '0',
DQ7 => DDR_DQ(23),
NC14 => '1',
VDDQ15 => '1',
LDQS => DDR_DQS(2),
NC17 => '1',
VDD18 => '1',
NC19 => '1',
LDM => DDR_DM(2),
WEB => DDR_WEn,
CASB => DDR_CASn,
RASB => DDR_RASn,
CSB => DDR_CSn,
NC25 => '1',
BA0 => DDR_BankAddr(0),
BA1 => DDR_BankAddr(1),
A10 => DDR_Addr(10),
A0 => DDR_Addr(0),
A1 => DDR_Addr(1),
A2 => DDR_Addr(2),
A3 => DDR_Addr(3),
VDD33 => '1',
VSS34 => '0',
A4 => DDR_Addr(4),
A5 => DDR_Addr(5),
A6 => DDR_Addr(6),
A7 => DDR_Addr(7),
A8 => DDR_Addr(8),
A9 => DDR_Addr(9),
A11 => DDR_Addr(11),
NC42 => '1',
NC43 => '1',
CKE => DDR_CKE,
CLK => DDR_Clk,
CLKB => DDR_CLKn,
UDM => DDR_DM(3),
VSS48 => '0',
VREF => '1',
NC50 => '1',
UDQS => DDR_DQS(3),
VSSQ52 => '0',
NC53 => '1',
DQ8 => DDR_DQ(24),
VDDQ55 => '1',
DQ9 => DDR_DQ(25),
DQ10 => DDR_DQ(26),
VSSQ58 => '0',
DQ11 => DDR_DQ(27),
DQ12 => DDR_DQ(28),
VDDQ61 => '1',
DQ13 => DDR_DQ(29),
DQ14 => DDR_DQ(30),
VSSQ64 => '0',
DQ15 => DDR_DQ(31),
VSS66 => '0'
);
DDR_CLK_FB <= DDR_CLK;
----------------------------------------------------------------------
-------------------------------------------------------------------------
-- START USER CODE (Do not remove this line)
tb_clk : PROCESS
BEGIN
LVPECLK_n <= '0';
LVPECLK_p <= '1';
wait for 10 ns;
LVPECLK_n <= '1';
LVPECLK_p <= '0';
wait for 10 ns;
END PROCESS;
end architecture STRUCTURE;
