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В чем тpабл?
generic(N:natural:=7);
...........................
port X: in unsigned(N downto 0);
.....................................
signal regx: unsigned(2*N+1 downto 0);
.......................................
regx(2*N+1 downto N+1)<=(others=>X(n));
regx(N downto 0)<=X;
Имеем pугательства компиллятоpа в Xilinx
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