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module bin2_bcd_reg (clk, bin, bcd, enable_rd_bcd); // U.Tietze - Ch.Schenk page 321
input clk;
input [19:0] bin;
output [27:0] bcd;
output enable_rd_bcd;
reg [4:0] ct_bit;
reg [19:0] bin_rg;
reg [27:0] bcd_rg;
reg [27:0] bcd;
reg enable_rd_bcd;
function [3:0] correct ;
input [3:0] decade;
begin
correct = (decade > 4) ? (decade + 4'd3) : decade;
end
endfunction
always @ (posedge clk)
begin
enable_rd_bcd = (ct_bit == 5'd0);
if (ct_bit == 5'd0) begin
bcd = bcd_rg;
bcd_rg = 28'd0;
bin_rg = bin;
ct_bit = 5'd20; end
else begin
bcd_rg[3:0] = correct(bcd_rg[3:0]);
bcd_rg[7:4] = correct(bcd_rg[7:4]);
bcd_rg[11:8] = correct(bcd_rg[11:8]);
bcd_rg[15:12] = correct(bcd_rg[15:12]);
bcd_rg[19:16] = correct(bcd_rg[19:16]);
bcd_rg[23:20] = correct(bcd_rg[23:20]);
bcd_rg[27:24] = correct(bcd_rg[27:24]);
bcd_rg = {bcd_rg[26:0], bin_rg[19]};
bin_rg = (bin_rg << 1);
ct_bit = ct_bit - 1'b1; end
end
endmodule