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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
ENTITY bufcanal IS
port (
addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
we: IN std_logic);
END bufcanal;
ARCHITECTURE bufcanal_a OF bufcanal IS
-- synopsys translate_off
component wrapped_bufcanal
port (
addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
we: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_bufcanal use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
generic map(
c_sinit_value => "0",
c_has_en => 0,
c_reg_inputs => 0,
c_yclk_is_rising => 1,
c_ysinit_is_high => 1,
c_ywe_is_high => 1,
c_yprimitive_type => "256x16",
c_ytop_addr => "1024",
c_yhierarchy => "hierarchy1",
c_has_limit_data_pitch => 0,
c_has_rdy => 0,
c_write_mode => 0,
c_width => 16,
c_yuse_single_primitive => 1,
c_has_nd => 0,
c_has_we => 1,
c_enable_rlocs => 0,
c_has_rfd => 0,
c_has_din => 1,
c_ybottom_addr => "0",
c_pipe_stages => 0,
c_yen_is_high => 1,
c_depth => 256,
c_has_default_data => 1,
c_limit_data_pitch => 8,
c_has_sinit => 0,
c_yydisable_warnings => 1,
c_mem_init_file => "mif_file_16_1",
c_default_data => "0",
c_ymake_bmm => 0,
c_addr_width => 8);
-- synopsys translate_on
BEGIN
-- synopsys translate_off
U0 : wrapped_bufcanal
port map (
addr => addr,
clk => clk,
din => din,
dout => dout,
we => we);
-- synopsys translate_on
END bufcanal_a;
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