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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity del_clk is
port (
set : in STD_LOGIC;
out_clk : out STD_LOGIC;
clk : in STD_LOGIC;
prog : in STD_LOGIC_VECTOR (15 downto 0)
);
end del_clk;
architecture del_clk of del_clk is
signal set_r, set_rr : STD_LOGIC;
signal start_r, start_rr : STD_LOGIC;
signal count_del : STD_LOGIC_VECTOR (15 downto 0);
begin
process (clk)
begin
if clk'event and clk = '1' then
set_r <= set;
set_rr <= set_r;
start_rr <= '0';
if set_r = '1' and set_rr = '0' then
count_del <= (others => '0');
start_r <= '0';
end if;
if unsigned(count_del) < unsigned(prog) then
count_del <= std_logic_vector(unsigned(count_del) + 1);
else
start_r <= '1';
if start_r = '0' then
start_rr <= '1';
end if;
end if;
end if;
end process;
out_clk <= start_rr;
end del_clk;
И тест к нему
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity del_clk_tb is
end del_clk_tb;
architecture TB_ARCHITECTURE of del_clk_tb is
component del_clk
port(
set : in std_logic;
out_clk : out std_logic;
clk : in std_logic;
prog : in std_logic_vector(15 downto 0) );
end component;
signal set : std_logic := '0';
signal clk : std_logic := '0';
signal prog : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(10#20#,16));
signal out_clk : std_logic;
begin
UUT : del_clk
port map (
set => set,
out_clk => out_clk,
clk => clk,
prog => prog
);
clk <= not clk after 5 ns;
set <= '0' after 1ns, '1' after 26 ns, '0' after 57 ns, '1' after 101 ns, '0' after 123 ns;
end TB_ARCHITECTURE;
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