[an error occurred while processing this directive]
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity div5 is
Port (
clk : in std_logic;
count : buffer std_logic_vector (7 downto 0):="00000000");
end div5;
architecture Behavioral of div5 is
begin
process (clk)
begin
if clk='1' and clk'event then
count <= count + 1;
end if;
end process;
end Behavioral;