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Квартус предупреждает как и другие сигнтезаторы:
CAUSE: In an Always Construct at the specified location in a Verilog Design File (.v), you read the value of the specified variable. However, you did not include the variable in the Always Construct's Event Control (sensitivity list). Although this omission does not affect the logic generated by Quartus II Integrated Synthesis, it may cause the design's simulated behavior to differ from the behavior of the synthesized logic
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