|
|
Неточность вышла с разрядностью сдвигающего регистра
module del25
(
input clk_50,
input start_n,
output clk_2
);
reg [2:0] shift_rg;
reg [4:0] ct_a;
reg temp;
always @(posedge clk_50) begin
shift_rg <= {shift_rg[1:0], start_n};
if (~shift_rg[2] & shift_rg[1]) ct_a <= 5'd0;
else if (ct_a == 5'd24) ct_a <= 5'd0;
else ct_a <= ct_a + 1'b1;
if (~shift_rg[2] & shift_rg[1]) temp <= 1'b0;
else if (ct_a == 5'd24) temp <= 1'b0;
else if (ct_a == 5'd12) temp <= 1'b1; end
assign clk_2 = temp;
endmodule
|
|
E-mail: 
info@telesys.ru
