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топовый
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity message is
port (
RESET : in std_logic;
CLK : in std_logic;
MESS_ENABLE : in std_logic; -- Signal to start the message out sequence.
MESS_DONE : out std_logic; -- Signals the completion of the output message.
-- The current state machine will not get set this output.
-- RS-232 driver signals.
SER_IN : in STD_LOGIC; -- Serial input signal.
SER_OUT : out STD_LOGIC; -- Serial output signal.
SER_RTS : in STD_LOGIC;
SER_CTS : out STD_LOGIC
);
end message;
architecture rtl of message is
-- Transmit Byte
component UART_TX
port (
RESET: in std_logic; -- RESET
BAUDCLK: in std_logic; -- This clock is the BUAD rate clock
DATA: in std_logic_vector(7 downto 0); -- DATA to be sent
SER_OUT: out std_logic; -- Serial output line
SEND_DATA: in std_logic; -- Trigger serial out
BUSY: out std_logic -- Transmitting Flag
);
end component;
-- Recieve Byte
component UART_RX
port (
RESET: in std_logic; -- RESET
X16CLK: in std_logic; -- This clock is 16 time as fast as baud rate clock
DATA: out std_logic_vector(7 downto 0); -- The output on these signals is valid on the rising DATA_READY signal
SER_IN: in std_logic; -- Serial input line
DATA_READY: out std_logic -- This signal goes high one clock after DATA is valid. Signal is active for one clock.
);
end component;
type STATES is (StartTX,WaitTX,WaitTXDone,NextTX,Done,ECHO1,ECHO2,ECHO3);
signal mode : STATES;
signal DATA_OUT,DATA_IN: std_logic_vector(7 downto 0); -- DATA to be sent
signal SEND_DATA,DATA_READY: std_logic; -- Trigger serial out
signal BUSY: std_logic; -- Transmitting Flag
signal BAUDcount: std_logic_vector(3 downto 0);
signal BAUD19200 : std_logic;
signal X16count: std_logic_vector(15 downto 0);
signal X16CLK : std_logic;
---------------------------
-- Output message
-- AVNET DESIGN SERVICES
-- design@ads.avnet.com
-- 1.800.585.1602
-- www.ads.avnet.com
-- KOKERBOOM Development Board
subtype ROM_WORD is STD_LOGIC_VECTOR (7 downto 0);
type ROM_TABLE is array (0 to 112) of ROM_WORD;
constant ROM: ROM_TABLE := ROM_TABLE'(
ROM_WORD'("00001010"), -- 0x0A
ROM_WORD'("00001101"), -- 0x0D
ROM_WORD'("01000001"), -- A
ROM_WORD'("01010110"), -- V
ROM_WORD'("01001110"), -- N
ROM_WORD'("01000101"), -- E
ROM_WORD'("01010100"), -- T
ROM_WORD'("00100000"), --
ROM_WORD'("01000100"), -- D
ROM_WORD'("01000101"), -- E
ROM_WORD'("01010011"), -- S
ROM_WORD'("01001001"), -- I
ROM_WORD'("01000111"), -- G
ROM_WORD'("01001110"), -- N
ROM_WORD'("00100000"), --
ROM_WORD'("01010011"), -- S
ROM_WORD'("01000101"), -- E
ROM_WORD'("01010010"), -- R
ROM_WORD'("01010110"), -- V
ROM_WORD'("01001001"), -- I
ROM_WORD'("01000011"), -- C
ROM_WORD'("01000101"), -- E
ROM_WORD'("01010011"), -- S
ROM_WORD'("00001010"), -- 0x0A
ROM_WORD'("00001101"), -- 0x0D
ROM_WORD'("01100100"), -- d
ROM_WORD'("01100101"), -- e
ROM_WORD'("01110011"), -- s
ROM_WORD'("01101001"), -- i
ROM_WORD'("01100111"), -- g
ROM_WORD'("01101110"), -- n
ROM_WORD'("01000000"), -- @
ROM_WORD'("01100001"), -- a
ROM_WORD'("01100100"), -- d
ROM_WORD'("01110011"), -- s
ROM_WORD'("00101110"), -- .
ROM_WORD'("01100001"), -- a
ROM_WORD'("01110110"), -- v
ROM_WORD'("01101110"), -- n
ROM_WORD'("01100101"), -- e
ROM_WORD'("01110100"), -- t
ROM_WORD'("00101110"), -- .
ROM_WORD'("01100011"), -- c
ROM_WORD'("01101111"), -- o
ROM_WORD'("01101101"), -- m
ROM_WORD'("00001010"), -- 0x0A
ROM_WORD'("00001101"), -- 0x0D
ROM_WORD'("00110001"), -- 1
ROM_WORD'("00101110"), -- .
ROM_WORD'("00111000"), -- 8
ROM_WORD'("00110000"), -- 0
ROM_WORD'("00110000"), -- 0
ROM_WORD'("00101110"), -- .
ROM_WORD'("00110101"), -- 5
ROM_WORD'("00111000"), -- 8
ROM_WORD'("00110101"), -- 5
ROM_WORD'("00101110"), -- .
ROM_WORD'("00110001"), -- 1
ROM_WORD'("00110110"), -- 6
ROM_WORD'("00110000"), -- 0
ROM_WORD'("00110010"), -- 2
ROM_WORD'("00001010"), -- 0x0A
ROM_WORD'("00001101"), -- 0x0D
ROM_WORD'("01110111"), -- w
ROM_WORD'("01110111"), -- w
ROM_WORD'("01110111"), -- w
ROM_WORD'("00101110"), -- .
ROM_WORD'("01100001"), -- a
ROM_WORD'("01100100"), -- d
ROM_WORD'("01110011"), -- s
ROM_WORD'("00101110"), -- .
ROM_WORD'("01100001"), -- a
ROM_WORD'("01110110"), -- v
ROM_WORD'("01101110"), -- n
ROM_WORD'("01100101"), -- e
ROM_WORD'("01110100"), -- t
ROM_WORD'("00101110"), -- .
ROM_WORD'("01100011"), -- c
ROM_WORD'("01101111"), -- o
ROM_WORD'("01101101"), -- m
ROM_WORD'("00001010"), -- 0x0A
ROM_WORD'("00001101"), -- 0x0D
ROM_WORD'("01001011"), -- K
ROM_WORD'("01001111"), -- O
ROM_WORD'("01001011"), -- K
ROM_WORD'("01000101"), -- E
ROM_WORD'("01010010"), -- R
ROM_WORD'("01000010"), -- B
ROM_WORD'("01001111"), -- O
ROM_WORD'("01001111"), -- O
ROM_WORD'("01001101"), -- M
ROM_WORD'("00100000"), --
ROM_WORD'("01000100"), -- D
ROM_WORD'("01100101"), -- e
ROM_WORD'("01110110"), -- v
ROM_WORD'("01100101"), -- e
ROM_WORD'("01101100"), -- l
ROM_WORD'("01101111"), -- o
ROM_WORD'("01110000"), -- p
ROM_WORD'("01101101"), -- m
ROM_WORD'("01100101"), -- e
ROM_WORD'("01101110"), -- n
ROM_WORD'("01110100"), -- t
ROM_WORD'("00100000"), --
ROM_WORD'("01000010"), -- B
ROM_WORD'("01101111"), -- o
ROM_WORD'("01100001"), -- a
ROM_WORD'("01110010"), -- r
ROM_WORD'("01100100"), -- d
ROM_WORD'("00001010"), -- 0x0A
ROM_WORD'("00001101"), -- 0x0D
ROM_WORD'("00101101"), -- -
ROM_WORD'("00111110")); -- >
signal count: integer;
begin
-- RS-232 driver/receiver hardwired to be enabled and active.
--ENABLE_N <= '0';
--DEACTIVATE_N <= '1';
process(CLK,RESET)
begin
if RESET = '1' then
mode <= StartTX;
count <= 0;
MESS_DONE <= '0';
DATA_OUT <= "00000000";
SEND_DATA <= '0';
elsif CLK'event and CLK = '1' then
if MESS_ENABLE = '0' then
MESS_DONE <= '0'; -- wait.
else -- Send the message.
case mode is
when StartTX => -- Transmit the current byte.
MESS_DONE <= '0';
DATA_OUT <= ROM(count);
SEND_DATA <= '1';
mode <= WaitTX;
when WaitTX =>
MESS_DONE <= '0';
SEND_DATA <= '1';
if Busy = '0' then
mode <= WaitTX;
else
mode <= WaitTXDone;
end if;
when WaitTXDone =>
MESS_DONE <= '0';
SEND_DATA <= '0';
if Busy = '1' then
mode <= WaitTXDone;
else
mode <= NextTX;
end if;
when NextTX => -- Loop through the message.
MESS_DONE <= '0';
SEND_DATA <= '0';
if count = 113 then -- 15
mode <= ECHO1;
count <= 0;
else
count <= count +1;
mode <= StartTX;
end if;
when ECHO1 => -- Get byte
MESS_DONE <= '0';
if DATA_READY = '1' then
DATA_OUT <= DATA_IN;
SEND_DATA <= '1';
mode <= ECHO2;
else
mode <= ECHO1;
end if;
when ECHO2 => -- Sent Byte
MESS_DONE <= '0';
SEND_DATA <= '1';
if Busy = '0' then
mode <= ECHO2;
else
mode <= ECHO3;
end if;
when ECHO3 =>
MESS_DONE <= '0';
SEND_DATA <= '0';
if Busy = '1' then
mode <= ECHO3;
else
mode <= ECHO1;
end if;
when Done => -- Can't get here.
SEND_DATA <= '0';
MESS_DONE <= '1';
mode <= StartTX;
when others =>
SEND_DATA <= '0';
MESS_DONE <= '1';
mode <= StartTX;
end case;
end if;
end if;
end process;
-- Generate a communication clock and a sampling clock - 19200 baud
-- UART Baudrate constant
--
-- C_BAUD_COUNT = { [ 48M / (baudrate x 16)] / 2 } - 1
--
---------------------------------------------------------------------
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"4D" ; --for 19200 Baudrate @48MHz
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"40" ; --for 19200 Baudrate @40MHz
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"81" ; --for 9600 Baudrate @40MHz
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"96" ; --for 9600 Baudrate @48MHz
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"20" ; --for 9600 Baudrate @10MHz
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"50" ; --for 9600 Baudrate @25MHz
--constant C_BAUD_COUNT : std_logic_vector(7 downto 0) := X"2A" ; --for 19200 Baudrate @27MHz
process(CLK,RESET)
begin
if RESET = '1' then
X16count <= "0000000000000000";
BAUD19200 <= '0';
BAUDcount <= "0000";
X16CLK <= '0';
elsif CLK'event and CLK = '1' then
if X16count = 64 then --64 (40MHz oscillator), 74 (48MHz osc) or 81 (50MHz osc)
X16CLK <= not X16CLK;
X16count <= "0000000000000000";
if BAUDcount = 15 then
BAUD19200 <= not BAUD19200;
BAUDcount <= "0000";
else
BAUDcount <= BAUDcount + 1;
end if;
else
X16count <= X16count +1;
end if;
end if;
end process;
inst_uart_tx: UART_TX port map(RESET,BAUD19200,DATA_OUT,SER_OUT,SEND_DATA,BUSY);
inst_uart_rx: UART_RX port map(RESET,X16CLK,DATA_IN,SER_IN,DATA_READY);
end rtl;
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