[an error occurred while processing this directive]
|
http://rapidshare.de/files/18486318/bks.rar.html - 35 мегабайт
Verilog HDL - A Guide To Digital Design And Synthesis - Palnitkar.rar
The Verilog Hardware Description Language - Thomas, Moorby.rar
HDL Chip Design - Smith.rar
Verilog HDL Synthesis - A Practical Primer - Bhasker.djvu
E-mail: info@telesys.ru