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Verilog 2001 support has been extended to support indexed part select
expressions (+: and -:), which use a variable range to provide access to a word or part of a word. The software knows the size of the operators at compile time, but the index expression range can remain dynamic. You can use the partial select operators to index any nonscalar variable. The syntax to use these operators is described below.
my_vector [base_expression +: width_expression]
my_vector [base_expression -: width_expression]
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SystemVerilog Operators
Operator Example Same as
A += 2; A = A + 2;
B -= B; B = B - A;
C *= B; C = C * B;
D /= C; D = D / C;
E %= D; E = E % D;
F &= E; F = F & E;
G |= F; G = G | F;
H ^= G; H H ^ G;
I <<= H; I = I << H;
J >>= I; J = J >> I;
K <<<=J; K = K <<< J;
L >>>=K; L = L >>> K;
In addition, SystemVerilog also introduces increment/decrement operators
i++, i--, ++i, and --i.
A++; // same as A = A + 1;
B--; // same as A = A - 1;
++A; // Increment first and then use A;
--A; // Decrement first and then use A;
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