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А чего в него вникать. Копировать надо.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
generic (MAX : integer := 15);
port(
C, CLR : in std_logic;
Q : out integer range 0 to MAX-1);
end counter;
architecture archi of counter is
signal cnt : integer range 0 to MAX-1;
begin
process (C, CLR)
begin
if (CLR='1') then
cnt <= 0;
elsif (rising_edge(C)) then
cnt <= (cnt + 1) mod (MAX) ;
end if;
end process;
Q <= cnt;
end archi;
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