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genmem Command-Line Usage: Option: Description: asynram Asynchronous RAM -vhdl Generate Synopsys-compatible VHDL output (the default if no options are used) This example generates a 256 by 15 asynchronous ROM model, asyn_rom_256x15.vhd,
E-mail:
info@telesys.ru
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genmem
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asynrom Asynchronous ROM
synram Synchronous RAM
synrom Synchronous ROM
csdpram Cycle-shared dual-port RAM
asyndpram Asynchronous dual-port RAM
syndpram Synchronous dual-port RAM
csfifo Cycle-shared FIFO
scfifo Single-clock FIFO
dcfifo Dual-clock FIFO
the size of the memory, which consists of two values
separated by the letter 'x':
-verilog Generate Synopsys-compatible Verilog HDL output
-viewlogic Generate VHDL model for Viewlogic
-o Overwrite the output file
Example: genmem asynrom 256x15
a VHDL Component Declaration template, asyn_rom_256x15.cmp, and a timing
technology library, asyn_rom_256x15.lib
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