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Под рукой только хилинхова двупортовая блокрам
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-- Dual port (Xilinx BLOCK) RAM.
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity BlkRAMDP is
generic(DataWidth_g : in positive := 8;
AdrWidth_g : in positive := 11
);
port (
ClkA : in std_logic;
ADRA : in unsigned(AdrWidth_g-1 downto 0);
WEA : in std_logic;
DIA : in std_logic_vector(DataWidth_g-1 downto 0);
ClkB : in std_logic;
ADRB : in unsigned(AdrWidth_g-1 downto 0);
REB : in std_logic;
DOB : out std_logic_vector(DataWidth_g-1 downto 0)
);
end entity BlkRAMDP;
architecture BlkRAMDP_arch of BlkRAMDP is
constant ramdepth_c : positive := 2**AdrWidth_g;
type ram_t is array (ramdepth_c-1 downto 0) of std_logic_vector(DataWidth_g-1 downto 0);
signal RAM : ram_t;
begin
writeA_p: process (ClkA) is
begin
if rising_edge(ClkA) then
if (WEA = '1') then
RAM(TO_INTEGER(ADRA)) <= DIA;
end if;
end if;
end process writeA_p;
readB_p: process (ClkB) is
begin
if rising_edge(ClkB) then
if (REB = '1') then
DOB <= RAM(TO_INTEGER(ADRB));
end if;
end if;
end process readB_p;
end architecture BlkRAMDP_arch;
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