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library IEEE;
use IEEE.std_logic_1164.all;entity pipa is
port
(
sck : in std_logic;
ssel : in std_logic;
mosi : in std_logic;
miso : out std_logic;
clr : in std_logic;
in_data : in std_logic_vector(23 downto 0);
out_data : out std_logic_vector(23 downto 0)
);
end entity pipa;architecture pipa of pipa is
signal in_shift_reg : std_logic_vector(23 downto 0);
signal out_shift_reg : std_logic_vector(23 downto 0);
signal load : std_logic;
begin
out_proc :
process (ssel, clr) is
begin
if (clr = '0') then
out_data <= (others => '0');
elsif (falling_edge(ssel)) then
out_data <= in_shift_reg;
end if;
end process out_proc;
load_proc :
process (sck, ssel, clr) is
begin
if (ssel = '0')and(clr = '0') then
load <= '0';
elsif (rising_edge(sck)) then
load <= '1';
end if;
end process load_proc;
MISO <= out_shift_reg(23);
proc1 :
process (sck, clr) is
begin
if (clr = '0') then
out_shift_reg <= (others => '0');
in_shift_reg <= (others => '0');
elsif (rising_edge(sck)) then
if (load = '0') then
out_shift_reg <= in_data;
elsif (ssel = '1') then
for i in 23 downto 1 loop
out_shift_reg(i) <= out_shift_reg(i-1);
end loop;
out_shift_reg(0) <= '0';
for i in 1 to 23 loop
in_shift_reg(i) <= in_shift_reg(i-1);
end loop;
in_shift_reg(0) <= MOSI;
end if;
end if;
end process proc1;
end architecture pipa;
Не верилог канечно но думаю понятно будет как работет
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