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Вот Код:
module IO_SPI(SSEL,SCK,MOSI,MISO,in_port,out_port,GlobalClr);
input SSEL,MOSI,GlobalClr;
input SCK; /* synthesis clock = 1 */
output MISO;
input[23:0]in_port;
output[23:0]out_port;
//reg[23:0]out_port;
reg[4:0]bit_cntr;
reg[23:0]byte;
always@(negedge SCK, posedge SSEL)
begin
if(SSEL)
begin
bit_cntr = 0;
end
else bit_cntr = bit_cntr + 5'b00001;
end
/*
always@(bit_cntr,GlobalClr)
begin
if(GlobalClr != 1'b1)
begin
out_port <= 24'hffffff;
end
else
begin
if(bit_cntr == 24)
begin
out_port <= byte;
end
end
end
*/
assign out_port = (GlobalClr == 0)? 24'hffffff : ((bit_cntr == 24)? byte : out_port);
assign MISO = (SSEL==0) ? in_port[bit_cntr] : 1'bz;
always@(posedge SCK)
begin
byte[bit_cntr] = MOSI;
end
endmodule
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