Отправлено cdg 26 мая 2005 г. 11:27 В ответ на: ДЕЛЕНИЕ ДВУХ ПЕРЕМЕННЫХ на VHDL (например std_logic_vector) отправлено Geremy 26 мая 2005 г. 05:18

------------------------------------------------------------------------------------
--
-- Design unit generated by Aldec IP Core Generator, version 6.3.
-- Copyright (c) 2003-2004 by Aldec, Inc. All rights reserved.
--
------------------------------------------------------------------------------------
--
-- Created on Thursday 2005-05-26, 11:23:37
--
------------------------------------------------------------------------------------
-- Details:
--		Type: Signed fixed-point divider
--		Argument input A width: 8
--		Argument input B width: 8
--		Result output Q width: 8
--		Division by zero flag output DIVz active high
------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {fpdiv} architecture {fpdiv_arch}}
library IEEE;
use IEEE.std_logic_1164.all;
entity fpdiv is
	port (
		DIVz: out std_logic;
		A: in std_logic_vector(7 downto 0);
		B: in std_logic_vector(7 downto 0);
		Q: out std_logic_vector(7 downto 0)
	);
end fpdiv;
--}} End of automatically maintained section
library IEEE;
USe IEEE.std_logic_unsigned.all;
architecture fpdiv_arch of fpdiv is
	signal REMAINDERS0 : std_logic_vector(13 downto 0);
	signal REMAINDERS1 : std_logic_vector(13 downto 0);
	signal REMAINDERS2 : std_logic_vector(13 downto 0);
	signal REMAINDERS3 : std_logic_vector(13 downto 0);
	signal REMAINDERS4 : std_logic_vector(13 downto 0);
	signal REMAINDERS5 : std_logic_vector(13 downto 0);
	signal REMAINDERS6 : std_logic_vector(13 downto 0);
	signal REMAINDERS7 : std_logic_vector(13 downto 0);
	signal DIVISORS0 : std_logic_vector(13 downto 0);
	signal DIVISORS1 : std_logic_vector(13 downto 0);
	signal DIVISORS2 : std_logic_vector(13 downto 0);
	signal DIVISORS3 : std_logic_vector(13 downto 0);
	signal DIVISORS4 : std_logic_vector(13 downto 0);
	signal DIVISORS5 : std_logic_vector(13 downto 0);
	signal DIVISORS6 : std_logic_vector(13 downto 0);
	signal DIVISORS7 : std_logic_vector(13 downto 0);
	signal Q_TEMP : std_logic_vector(7 downto 0);
	signal Z0 : std_logic_vector(6 downto 0);
	signal Z1 : std_logic_vector(6 downto 0);
	signal ZERO : std_logic;
begin
	Z0 <= (others => '0');
	Z1 <= (others => '0');
	DIVISORS0 <= Z0 & B(6 downto 0);
	REMAINDERS7  <= Z1 & A(6 downto 0);
	DIVISORS1 <= DIVISORS0(12 downto 0) & '0';
	DIVISORS2 <= DIVISORS1(12 downto 0) & '0';
	DIVISORS3 <= DIVISORS2(12 downto 0) & '0';
	DIVISORS4 <= DIVISORS3(12 downto 0) & '0';
	DIVISORS5 <= DIVISORS4(12 downto 0) & '0';
	DIVISORS6 <= DIVISORS5(12 downto 0) & '0';
	DIVISORS7 <= DIVISORS6(12 downto 0) & '0';
	Q_TEMP(0) <= '1' when (REMAINDERS1 >= DIVISORS0) else '0';
	Q_TEMP(1) <= '1' when (REMAINDERS2 >= DIVISORS1) else '0';
	Q_TEMP(2) <= '1' when (REMAINDERS3 >= DIVISORS2) else '0';
	Q_TEMP(3) <= '1' when (REMAINDERS4 >= DIVISORS3) else '0';
	Q_TEMP(4) <= '1' when (REMAINDERS5 >= DIVISORS4) else '0';
	Q_TEMP(5) <= '1' when (REMAINDERS6 >= DIVISORS5) else '0';
	Q_TEMP(6) <= '1' when (REMAINDERS7 >= DIVISORS6) else '0';
	Q_TEMP(7) <= A(7) xor B(7);
	REMAINDERS6 <= REMAINDERS7 - DIVISORS6 when Q_TEMP(6) = '1' else REMAINDERS7;
	REMAINDERS5 <= REMAINDERS6 - DIVISORS5 when Q_TEMP(5) = '1' else REMAINDERS6;
	REMAINDERS4 <= REMAINDERS5 - DIVISORS4 when Q_TEMP(4) = '1' else REMAINDERS5;
	REMAINDERS3 <= REMAINDERS4 - DIVISORS3 when Q_TEMP(3) = '1' else REMAINDERS4;
	REMAINDERS2 <= REMAINDERS3 - DIVISORS2 when Q_TEMP(2) = '1' else REMAINDERS3;
	REMAINDERS1 <= REMAINDERS2 - DIVISORS1 when Q_TEMP(1) = '1' else REMAINDERS2;
	REMAINDERS0 <= REMAINDERS1 - DIVISORS0 when Q_TEMP(0) = '1' else REMAINDERS1;
	ZERO <= '1' when B(6 downto 0) = Z1 else '0';
	DIVz <= '1' when ZERO = '1' else '0';
	Q <= (others => '0') when ZERO = '1' else Q_TEMP;
end fpdiv_arch;

• Ответ: большое спасибо — Geremy   (10.06.2005 04:25 217.74.161.201, пустое)