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module COUNT
(
input clockCnt, signalSet,
input [7:0] signal,
output reg [7:0] cnt
);
reg flag, tmp ;
reg [7:0] loadCnt ;
always @(posedge clockCnt)
if (flag) cnt <= loadCnt; else cnt <= cnt + 1 ;
always @(posedge clockCnt) loadCnt <= signal ;
always @(posedge signalSet, posedge tmp) if (tmp) flag <= 0 ; else flag <= 1 ;
always @(posedge clockCnt, negedge flag) if(~flag) tmp <= 0 ; else tmp <= 1 ;
endmodule
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