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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;entity strob_former is
port
(
reset :in std_logic;
clock :in std_logic;
strob :out std_logic
);
end strob_former;architecture behave of strob_former is
signal count : std_logic_vector (4 downto 0);
signal strob_i : std_logic;
signal strob_o : std_logic;
begin
process (clock, reset)
begin
if (reset = '1') then
count <= (others => '0');
elsif (clock'event and clock = '1') then
count <= count + '1';
end if;
end process;strob_i <= '1' when count = "00000" else '0';-- Registered STROBE for avoiding glitch
process (clock, reset)
begin
if (reset = '1') then
strob_o <= '0';
elsif (clock'event and clock = '1') then
strob_o <= strob_i;
end if;
end process;strob <= strob_o;
end behave;
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