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A register is an abstraction of a data storage element. The keyword for the register data type
is REG. A register stores a value from one assignment to the next. An assignment statement
in a procedure acts as a trigger that changes the value in the register. The Verilog language
has powerful constructs that allow you to control when and if these assignment statements
are executed.
т.е. всеже изначально переменная типа РЕГ предназначена для хранения значения переменной.
.или я что-то не так понимаю?
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