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VLSI Design Tools
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In 500 lines of colorForth these tools provide everything required to design a chip. They are derived from an earlier version called OKAD that successfully generated many versions of Forth microprocessor chips.
Description
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A chip requires the placement and interconnect routing for a heirarchy of gates, cells, pads and floorplan. This is described using a coarse-grid coordinate system of boxes called "tiles". Each tile has 6 layers and can describe a trace, contact or transistor. Tile size is chosen to enforce the geometric design rules for a particular process.
A language for describing this is carefully designed to translate easily into GDS II. It includes positioning wells and diffusion, placing polysilicon to form a transistor, adding contacts to source and drain and routing traces amongst layers. This is a geometric description of a chip, including more information than a schematic provides.
E-mail: 
info@telesys.ru
