Отправлено A_S_N 19 января 2005 г. 19:45 В ответ на: REM, MOD, Двоично-десятичный счетчик. VHDL. Помогите сделать.... отправлено Compana 18 января 2005 г. 23:05

Собственно subj...

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity Counter is
	generic (DIGIT:integer:= 7;	-- Maximum position number in decimal radix
		 WIDTH:integer:= 4;	-- One digit binary width
		 BASE :integer:=10);	-- Counter radix
	port(         
		Clk : in  std_logic;
		Reset:in  std_logic;
		DO :  out std_logic_vector(WIDTH*DIGIT-1 downto 0)
	     );       
end entity Counter;
architecture Struct of Counter is
--========== Type determination ===============--
constant BINARY_SIZE:integer:=WIDTH*DIGIT;
subtype Digit_Type   is integer range 0 to BASE-1;
subtype Number_Type  is integer range 0 to DIGIT-1;
subtype Decimal_Type is std_logic_vector (WIDTH-1 downto 0);
subtype Output_Type  is std_logic_vector (BINARY_SIZE-1 downto 0);
type Dec_Count_Type  is record
	CY: std_logic;
	DO: Digit_Type;
end record Dec_Count_Type;
type Counter_Type is array (Number_Type) of Digit_Type;
--========= Constant determination ============--
constant SET_CY: 	Dec_Count_Type:=('1',0);
constant INIT_DIGIT: 	Digit_Type:=(0);
constant INIT_COUNTER:	Counter_Type:=(others=>INIT_DIGIT);
--============== Using function ================--
function decimal_digit (Prev: in Digit_Type; CE: in std_logic) return  Dec_Count_Type is
variable C: Dec_Count_Type;
begin
	C:=('0',Prev);
	if CE='1' then
		if Prev=Digit_Type'high then C	 :=SET_CY;
					else C.DO:=Prev + 1;
		end if;
	end if;
	return C;
end function decimal_digit;
function decimal_number (Prev: in Counter_Type) return  Counter_Type is
variable C: Counter_Type;
variable CY:Dec_Count_Type;
begin
	C    :=Prev;
	CY.CY:='1';
C_INST:	for i in 0 to Number_Type'high loop
		CY:= decimal_digit (C(i), CY.CY);
		C(i):=CY.DO;
		end loop C_INST;
	return C;
end function decimal_number;
function dec_to_std_logic_vector (Dec: in Counter_Type) return  Output_Type is
variable O:	Output_type;
begin
	O:=(others=>'0');
O_INST:	for i in 0 to Number_Type'high loop 
	O((i+1)*WIDTH-1 downto i*WIDTH):=CONV_STD_LOGIC_VECTOR(Dec(i),WIDTH);
	end loop O_INST;
	return O;
end function dec_to_std_logic_vector;
--=============== Using signal =================--
signal 	 Cr: Counter_Type;
begin
SYNC:process(Reset,Clk)
variable Cv: Counter_Type;
begin
	if Reset='1' then Cv:=INIT_COUNTER; elsif rising_edge(Clk) then Cv:=decimal_number(Cr); end if;
	Cr<=Cv;
	DO<=dec_to_std_logic_vector(Cv);	
end process SYNC;
end architecture Struct;

Результаты сентеза для Leonardo:

Device : 2s50eft256
Slice : 34 (3.91%)
Clock : 98.1 MHz

Device : EP1C3T100C
LCs : 47 (1.62%)
Clock : 155.3 MHz