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library IEEE;
use IEEE.STD_LOGIC_1164.all;
library LPM;
use LPM.lpm_components.ALL;
entity bcd_cnt is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dig : out STD_LOGIC_VECTOR(27 downto 0)
);
end bcd_cnt;
architecture bcd_cnt of bcd_cnt is
signal cin:std_logic_vector(6 downto 0);
begin
gen_loop:for i in 0 to 6 generate
dig0:if i=0 generate
cnt_bcd:lpm_counter
generic map(
LPM_WIDTH => 4,
LPM_MODULUS =>10
)
port map(
clock =>clk,
aclr => reset,
q =>dig(3 downto 0),
cout =>cin(0)
);
end generate;
digx:if i>0 generate
cnt_bcd:lpm_counter
generic map(
LPM_WIDTH => 4,
LPM_MODULUS =>10
)
port map(
clock =>clk,
aclr => reset,
q =>dig(i*4+3 downto i*4),
cin =>cin(i-1),
cout =>cin(i)
);
end generate;
end generate;
end bcd_cnt;
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