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Думаю будет понятно.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
PACKAGE P_TYPE is
TYPE D16x32 is array(0 to 15) of std_logic_vector(31 downto 0);
END P_TYPE;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.P_TYPE.all;
.......
port( ....
DATA_SLAVE_IN : in D16x32;
....
);
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