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Я мельком глянул код и в подробностях не разбирался, но возникли следующее подозрения:
- код полностью асинхронный (что плохо уже само по себе), и синтезатор не знает чего ему делать. Synplify синтезировал, но с кучей жалоб, а на схеме вообще ничего нет, кроме портов.
Разбирайся с кодом, сделай его синхронным - это единственное, что я могу без детального анализа посоветовать.
Лог из Synplify выглядит следующим образом:
$ Start of Compile
#Tue Nov 09 09:27:06 2004
Synplicity VHDL Compiler, version Compilers 2.8.1, Build 015R, built Sep 2 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
@N:"C:\Temp\123.vhd":3:10:3:17|Top entity is set to SPI_Port.
VHDL syntax check successful!
Synthesizing work.spi_port.behave
@N: CD231 :"C:\Temp\123.vhd":15:28:15:29|Using onehot encoding for type instruct_type (none="1000")
@N: CD231 :"C:\Temp\123.vhd":20:32:20:33|Using onehot encoding for type bus_cycle_type (stand_by="10000")
@W:"C:\Temp\123.vhd":42:24:42:40|Index value 0 to 2147483647 could be out of prefix range 7 downto 0
@W:"C:\Temp\123.vhd":63:24:63:46|Index value 0 to 2147483647 could be out of prefix range 7 downto 0
@W: CD434 :"C:\Temp\123.vhd":19:25:19:29|Signal reset in the sensitivity list is not used in the process
Post processing for work.spi_port.behave
@W: CL162 :"C:\Temp\123.vhd":6:11:6:12|do is not assigned a value (floating)
@W: CL162 :"C:\Temp\123.vhd":5:16:5:17|rd is not assigned a value (floating)
@W: CL162 :"C:\Temp\123.vhd":5:11:5:14|miso is not assigned a value (floating)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register behavior.BusCycleDecode.bus_cycle_state_1(0 to 4)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register behavior.BusCycleDecode.code_cnt_1(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register behavior.BusCycleDecode.address_cnt_1(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register behavior.BusCycleDecode.data_cnt_1(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register behavior.BusCycleDecode.code_in_1(7 downto 0)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register behavior.BusCycleDecode.address_in_1(7 downto 0)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register address(7 downto 0)
@W: CL169 :"C:\Temp\123.vhd":28:12:28:13|Pruning Register instruct(0 to 3)
@W: CL169 :"C:\Temp\123.vhd":62:21:62:22|Pruning Register behavior.BusCycleDecode.bus_cycle_state_12(0 to 4)
@W: CL169 :"C:\Temp\123.vhd":62:21:62:22|Pruning Register behavior.BusCycleDecode.address_cnt_4(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":62:21:62:22|Pruning Register behavior.BusCycleDecode.address_in_2(7 downto 0)
@W: CL169 :"C:\Temp\123.vhd":62:21:62:22|Pruning Register behavior.BusCycleDecode.address_2(7 downto 0)
@W: CL169 :"C:\Temp\123.vhd":41:21:41:22|Pruning Register behavior.BusCycleDecode.bus_cycle_state_8(0 to 4)
@W: CL169 :"C:\Temp\123.vhd":41:21:41:22|Pruning Register behavior.BusCycleDecode.code_cnt_4(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":41:21:41:22|Pruning Register behavior.BusCycleDecode.code_in_2(7 downto 0)
@W: CL169 :"C:\Temp\123.vhd":41:21:41:22|Pruning Register behavior.BusCycleDecode.instruct_8(0 to 3)
@W: CL169 :"C:\Temp\123.vhd":33:21:33:22|Pruning Register behavior.BusCycleDecode.bus_cycle_state_3(0 to 4)
@W: CL169 :"C:\Temp\123.vhd":33:21:33:22|Pruning Register behavior.BusCycleDecode.code_cnt_2(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":33:21:33:22|Pruning Register behavior.BusCycleDecode.address_cnt_2(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":33:21:33:22|Pruning Register behavior.BusCycleDecode.data_cnt_1(30 downto 0)
@W: CL169 :"C:\Temp\123.vhd":33:21:33:22|Pruning Register behavior.BusCycleDecode.instruct_2(0 to 3)
@W: CL159 :"C:\Temp\123.vhd":4:11:4:14|Input mosi is unused
@W: CL159 :"C:\Temp\123.vhd":4:16:4:18|Input sck is unused
@W: CL159 :"C:\Temp\123.vhd":4:20:4:22|Input nce is unused
@W: CL159 :"C:\Temp\123.vhd":4:24:4:25|Input wr is unused
@W: CL159 :"C:\Temp\123.vhd":4:27:4:29|Input clk is unused
@W: CL159 :"C:\Temp\123.vhd":4:31:4:35|Input reset is unused
@W: CL159 :"C:\Temp\123.vhd":7:11:7:12|Input di is unused
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Altera Technology Mapper, version 7.7.0, Build 033R, built Sep 9 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
@N: MT210 |Because the design is Purely Combinational, Autoconstrain mode is TURNED OFF
Writing Analyst data base C:\Temp\rev_1\123.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to C:\Temp\rev_1\123.xrf
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Nov 09 09:27:07 2004
#
Top view: SPI_Port
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: NA
Interface Information
*********************
No IO constraint found
##### END OF TIMING REPORT #####]
##### START OF AREA REPORT #####[
Design view:work.SPI_Port(behave)
Selecting part EP1S10F780C5
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
I/O ATOMs: 0
Total LUTs: 0 of 10570 ( 0%)
Logic resources: 0 ATOMs of 10570 ( 0%)
ATOM count by mode:
normal: 0
arithmetic: 0
DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 6 blocks (48 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 1)
M4Ks: 0 (0% of 60)
M512s: 0 (0% of 94)
Total ESB: 0 bits
ATOMs using regout pin: 0
also using enable pin: 0
also using combout pin: 0
ATOMs using combout pin: 0
Number of Inputs on ATOMs: 0
Number of Nets: 16
##### END OF AREA REPORT #####]
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]
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