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ENTITY my IS
port (
a : in std_logic ;
b : in std_logic ;
c : out std_logic ;
d : out std_logic;
e : out std_logic
);
END ENTITY my;
architecture my_and of my is
--Variable w: std_logic;
begin
c <=NOT(a and b);
end my_and ;
architecture my_and1 of my is
begin
d <= not(a or b);
-- w := a ;
end my_and1;
architecture my_and2 of my is
begin
e <= (a or b);
-- w := a ;
end my_and2;
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