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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test_command is
port(
TCK : in std_logic;
CLK : in std_logic;
TMS : in std_logic;
TDI : in std_logic;
RST : in std_logic;
TDO : out std_logic;
led1: out std_logic;
led2: out std_logic
);
end test_command;
--}} End of automatically maintained section
architecture test_command of test_command is
signal reg0:std_logic_vector (3 downto 0);
signal reg1:std_logic_vector (3 downto 0);
signal reg2:std_logic_vector (3 downto 0);
signal com:std_logic;
signal TDO_1:std_logic;
signal TDO_2:std_logic;
begin
TDI_reg: process (TCK, RST) -- zapolhaet shift register
variable r_s:std_logic_vector (3 downto 0);
begin
if RST'event and RST = '1' then -- reset
for I in 3 downto 0 loop
r_s(I):='0';
end loop;
end if ;
if TCK'event and TCK='1' then
if TMS = '1' then
TDO_1<=r_s(3);
for I in 3 downto 1 loop
r_s(I):=r_s(I-1);
end loop;
r_s(0):=TDI;
reg0<=r_s;
end if;
end if;
end process TDI_reg;
parallel_reg: process(TMS) -- zapisali v register
begin
--if CLK'event and CLK='1' then
if TMS'event and TMS='0' then
reg1<=reg0;
end if;
-- end if;
end process parallel_reg;
Decode: process(CLK) -- Decodirovanie comandi
-- variable reg_m:std_logic_vector (3 downto 2);
begin
if CLK'event and CLK = '1' then
-- reg_m :=reg(3 downto 2);
C2: case reg1(3 downto 2) is
when "01" => led1 <= '1'; led2<='0'; com<='1'; reg2<=reg1;
when "10" => led1<='0'; led2 <= '1'; com<='1'; reg2<=reg1;
when "11" => led1<='1'; led2 <= '1'; com<='1'; reg2<=reg1;
when OTHERS => Null;
end case C2;
end if;
end process Decode;
TDO_reg: process(TCK,TMS)
variable shift_r:std_logic_vector (3 downto 0);
begin
if TMS'event and TMS ='1' then
shift_r:=reg2;
end if;
if TCK'event and TCK ='1' then
if TMS = '1' then
TDO_2<=shift_r(3);
for I in 3 downto 1 loop
shift_r(I):=shift_r(I-1);
end loop;
shift_r(0):='0';
end if;
end if;
end process TDO_reg;
TDO <= TDO_1 or TDO_2;
end test_command;
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