Отправлено -=Sergei=- 16 июня 2004 г. 10:38 В ответ на: Стоп, пока не правильно.... отправлено -=Sergei=- 16 июня 2004 г. 10:32

//-------------------------------------------------------------------------------------------------
//
// File : fpdiv.v
// Generated : Tue Jun 15 18:10:48 2004
// From : interface description file
// By : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description :
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
// and may be overwritten
//{module {fpdiv}}
module fpdiv ( Q ,A ,B ,DIVz );

input [10:0] A ;
wire [10:0] A ;
input [10:0] B ;
wire [10:0] B ;

output [10:0] Q ;
wire [10:0] Q ;
output DIVz ;
wire DIVz ;

//}} End of automatically maintained section

// -- Enter your statements here -- //
wire [21 : 0]REMAINDERS0;
wire [21 : 0]REMAINDERS1;
wire [21 : 0]REMAINDERS2;
wire [21 : 0]REMAINDERS3;
wire [21 : 0]REMAINDERS4;
wire [21 : 0]REMAINDERS5;
wire [21 : 0]REMAINDERS6 ;
wire [21 : 0]REMAINDERS7;
wire [21 : 0]REMAINDERS8;
wire [21 : 0]REMAINDERS9;
wire [21 : 0]REMAINDERS10;
wire [21 : 0]REMAINDERS11 ;

wire [21 : 0]DIVISORS0 ;
wire [21 : 0]DIVISORS1;
wire [21 : 0]DIVISORS2;
wire [21 : 0] DIVISORS3;
wire [21 : 0]DIVISORS4 ;
wire [21 : 0]DIVISORS5;
wire [21 : 0]DIVISORS6 ;
wire [21 : 0]DIVISORS7;
wire [21 : 0]DIVISORS8;
wire [21 : 0]DIVISORS9 ;
wire [21 : 0]DIVISORS10 ;
wire [21 : 0]DIVISORS11 ;

wire [10 : 0]Q_TEMP ;
wire [10 : 0]Z0;
wire [10 : 0]Z1;
wire ZERO ;

assign Z0 = 11'd0;
assign Z1 = 11'd0;
assign DIVISORS0 = {Z0 , B};
assign REMAINDERS11 = {Z1 , A};

assign DIVISORS1 = {DIVISORS0[20:0] , 1'b0};
assign DIVISORS2 = {DIVISORS1[20:0] , 1'b0};
assign DIVISORS3 = {DIVISORS2[20:0] , 1'b0};
assign DIVISORS4 = {DIVISORS3[20:0] , 1'b0};
assign DIVISORS5 = {DIVISORS4[20:0] , 1'b0};
assign DIVISORS6 = {DIVISORS5[20:0] , 1'b0};
assign DIVISORS7 = {DIVISORS6[20:0] , 1'b0};
assign DIVISORS8 = {DIVISORS7[20:0] , 1'b0};
assign DIVISORS9 = {DIVISORS8[20:0] , 1'b0};
assign DIVISORS10 ={ DIVISORS9[20:0] , 1'b0};
assign DIVISORS11 ={ DIVISORS10[20:0] , 1'b0};

assign Q_TEMP[0] = (REMAINDERS1 >= DIVISORS0)?1:0;
assign Q_TEMP[1] = (REMAINDERS2 >= DIVISORS1)?1:0;
assign Q_TEMP[2] = (REMAINDERS3 >= DIVISORS2)?1:0;
assign Q_TEMP[3] = (REMAINDERS4 >= DIVISORS3)?1:0;
assign Q_TEMP[4] = (REMAINDERS5 >= DIVISORS4)?1:0;
assign Q_TEMP[5] = (REMAINDERS6 >= DIVISORS5)?1:0;
assign Q_TEMP[6] = (REMAINDERS7 >= DIVISORS6)?1:0;
assign Q_TEMP[7] = (REMAINDERS8 >= DIVISORS7)?1:0;
assign Q_TEMP[8] = (REMAINDERS9 >= DIVISORS8)?1:0;
assign Q_TEMP[9] = (REMAINDERS10 >= DIVISORS9)?1:0;
assign Q_TEMP[10] = (REMAINDERS11 >= DIVISORS10)?1:0;

assign REMAINDERS10 = (Q_TEMP[10] == 1)?(REMAINDERS11 - DIVISORS10):REMAINDERS11;
assign REMAINDERS9 = (Q_TEMP[9] == 1)?(REMAINDERS10 - DIVISORS9):REMAINDERS10;
assign REMAINDERS8 = (Q_TEMP[8] == 1)?(REMAINDERS9 - DIVISORS8):REMAINDERS9;
assign REMAINDERS7 = (Q_TEMP[7] == 1)?(REMAINDERS8 - DIVISORS7):REMAINDERS8;
assign REMAINDERS6 = (Q_TEMP[6] == 1)?(REMAINDERS7 - DIVISORS6):REMAINDERS7;
assign REMAINDERS5 = (Q_TEMP[5] == 1)?(REMAINDERS6 - DIVISORS5):REMAINDERS6;
assign REMAINDERS4 = (Q_TEMP[4] == 1)?(REMAINDERS5 - DIVISORS4):REMAINDERS5;
assign REMAINDERS3 = (Q_TEMP[3] == 1)?(REMAINDERS4 - DIVISORS3):REMAINDERS4;
assign REMAINDERS2 = (Q_TEMP[2] == 1)?(REMAINDERS3 - DIVISORS2):REMAINDERS3;
assign REMAINDERS1 = (Q_TEMP[1] == 1)?(REMAINDERS2 - DIVISORS1):REMAINDERS2;
assign REMAINDERS0 = (Q_TEMP[0] == 1)?(REMAINDERS1 - DIVISORS0):REMAINDERS1;

assign ZERO = (B == Z1)?1:0;
assign DIVz = (ZERO == 1)?1:0;
assign Q = (ZERO == 1)?11'd0:Q_TEMP;

endmodule

• спасибо, разобрался — avsetaki   (16.06.2004 12:43, пустое)