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The Unexpected Results
Contestants were given 90 minutes using either Verilog or VHDL to create a gate netlist for the fastest fully synchronous loadable 9-bit increment-by-3 decrement-by-5 up/down counter that generated even parity, carry and borrow.
Of the 9 Verilog designers in the contest, only 1 didn't get to a final gate level netlist because he tried to code a look-ahead parity generator. Of the 8 remaining, 3 had netlists that missed on functional test vectors. The 5 Verilog designers who got fully functional gate-level designs were:
Larry Fiedler NVidea 3.90 nsec 1147 gates
Steve Golson Trilobyte Systems 4.30 nsec 1909 gates
Howard Landman HaL Computer 5.49 nsec 1495 gates
Mark Papamarcos EDA Associates 5.97 nsec 1180 gates
Ed Paluch Paluch & Assoc. 7.85 nsec 1514 gates
The surprize was that, during the same time, *none* of 5 VHDL designers in the contest managed to produce any gate level designs.
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UP DOWN DATA_IN | COUNT_OUT
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0 0 valid | load DATA_IN
0 1 don't care | (Q - 5)
1 0 don't care | (Q + 3)
1 1 don't care | Q unchanged
reg [9:0] cnt_up, cnt_dn;
reg [8:0] count_nxt;
always @(posedge clock)
begin
cnt_dn = count_out - 3'b 101; // synopsys label add_dn
cnt_up = count_out + 2'b 11; // synopsys label add_up
case ({up,down})
2'b 00 : count_nxt = data_in;
2'b 01 : count_nxt = cnt_dn;
2'b 10 : count_nxt = cnt_up;
2'b 11 : count_nxt = 9'bX; // SPEC NOT MET HERE!!!
default : count_nxt = 9'bX; // avoiding ambiguity traps
endcase
parity_out <= ^count_nxt;
carry_out <= up & cnt_up[9];
borrow_out <= down & cnt_dn[9];
count_out <= count_nxt;
end
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