|
|
Помогите мне, пожайлуста, кто-нибудь. Сама не могу додуматься. Переделываю Тест для АЛУ-программы. Ну не получается у меня. Мне нужно протестировать эту программу (написанную в VHDL) в программе/симуляторе "hamster". ПОЖАЙЛУСТА.
package dp32_types is
constant unit_delay : Time := 1 ns;
type bool_to_bit_table is array (boolean) of bit;
constant bool_to_bit : bool_to_bit_table;
subtype bit_32 is bit_vector(31 downto 0);
type bit_32_array is array (integer range <>) of bit_32;
function resolve_bit_32 (driver : in bit_32_array) return bit_32;
subtype bus_bit_32 is resolve_bit_32 bit_32;
subtype bit_8 is bit_vector(7 downto 0);
subtype CC_bits is bit_vector(2 downto 0);
subtype cm_bits is bit_vector(3 downto 0);
constant op_add : bit_8 := X"00";
constant op_sub : bit_8 := X"01";
constant op_mul : bit_8 := X"02";
constant op_div : bit_8 := X"03";
constant op_addq : bit_8 := X"10";
constant op_subq : bit_8 := X"11";
constant op_mulq : bit_8 := X"12";
constant op_divq : bit_8 := X"13";
constant op_land : bit_8 := X"04";
constant op_lor : bit_8 := X"05";
constant op_lxor : bit_8 := X"06";
constant op_lmask : bit_8 := X"07";
constant op_ld : bit_8 := X"20";
constant op_st : bit_8 := X"21";
constant op_ldq : bit_8 := X"30";
constant op_stq : bit_8 := X"31";
constant op_br : bit_8 := X"40";
constant op_brq : bit_8 := X"50";
constant op_bi : bit_8 := X"41";
constant op_biq : bit_8 := X"51";
function bits_to_int (bits : in bit_vector) return integer;
function bits_to_natural (bits : in bit_vector) return natural;
procedure int_to_bits (int : in integer; bits : out bit_vector);
end dp32_types;
----------------------------------------------------------
package body dp32_types is
constant bool_to_bit : bool_to_bit_table :=
(false => '0', true => '1');
function resolve_bit_32 (driver : in bit_32_array) return bit_32 is
constant float_value : bit_32 := X"0000_0000";
variable result : bit_32 := float_value;
begin
for i in 0 to 31 loop
result := result or driver(i);
end loop;
return result;
end resolve_bit_32;
function bits_to_int (bits : in bit_vector) return integer is
variable temp : bit_vector(31 downto 0);
variable result : integer := 0;
begin
if bits(31) = '1' then -- negative number
temp := not bits;
else
temp := bits;
end if;
for index in 0 to 31 loop -- sign bit of temp = '0'
result := result * 2 + bit'pos(temp(index));
end loop;
if bits(31) = '1' then
result := (-result) - 1;
end if;
return result;
end bits_to_int;
function bits_to_natural (bits : in bit_vector) return natural is
variable result : natural := 0;
begin
for index in 0 to 7 loop
result := result * 2 + bit'pos(bits(index));
end loop;
return result;
end bits_to_natural;
procedure int_to_bits (int : in integer; bits : out bit_vector) is
variable temp : integer;
variable result : bit_vector(0 to 31);
begin
if int < 0 then
temp := -(int+1);
else
temp := int;
end if;
for index in 0 to 31 loop
result(index) := bit'val(temp rem 2);
temp := temp / 2;
end loop;
if int < 0 then
result := not result;
result(31) := '1';
end if;
bits <= result;
end int_to_bits;
end dp32_types;
----------------------------------------------------------------------------------------------
package ALU_32_types is
type ALU_command is (disable, pass1, incr1,
add, subtract, multiply, divide,
log_and, log_or, log_xor, log_mask);
end ALU_32_types;
use work.dp32_types.all, work.ALU_32_types.all;
entity ALU_32 is
--generic (Tpd : Time := unit_delay);
port (operand1 : in bit_vector(31 downto 0);
operand2 : in bit_vector(31 downto 0);
result : out bit_vector(31 downto 0);
cond_code2: out bit;
cond_code1 : out bit;
cond_code0 : out bit;
command : in ALU_command);
end ALU_32;
architecture behaviour of ALU_32 is
begin
ALU_function: process (operand1, operand2, command)
variable a, b : integer;
variable temp_result : bit_32;
begin
case command is
when add | subtract | multiply | divide =>
a := bits_to_int(operand1);
b := bits_to_int(operand2);
when incr1 =>
a := bits_to_int(operand1);
b := 1;
when others => null;
end case;
case command is
when disable => null;
when pass1 => temp_result := operand1;
when log_and => temp_result := operand1 and operand2;
when log_or => temp_result := operand1 or operand2;
when log_xor => temp_result := operand1 xor operand2;
when log_mask => temp_result := operand1 and not operand2;
when add | incr1 =>
if b > 0 and a > integer'high-b then -- positive overflow
int_to_bits(((integer'low+a)+b)-integer'high-1, temp_result);
cond_code2 <= '1';-- after Tpd;
elsif b < 0 and a < integer'low-b then -- negative overflow
int_to_bits(((integer'high+a)+b)-integer'low+1, temp_result);
cond_code2 <= '1';-- after Tpd;
else
int_to_bits(a + b, temp_result);
cond_code2 <= '0';-- after Tpd;
end if;
when subtract =>
if b < 0 and a > integer'high+b then -- positive overflow
int_to_bits(((integer'low+a)-b)-integer'high-1, temp_result);
cond_code2 <= '1';-- after Tpd;
elsif b > 0 and a < integer'low+b then -- negative overflow
int_to_bits(((integer'high+a)-b)-integer'low+1, temp_result);
cond_code2 <= '1'; --after Tpd;
else
int_to_bits(a - b, temp_result);
cond_code2 <= '0'; --after Tpd;
end if;
when multiply =>
if ((a>0 and b>0) or (a<0 and b<0)) -- result positive
and (abs a > integer'high / abs b) then
-- positive overflow
int_to_bits(integer'high, temp_result);
cond_code2 <= '1';-- after Tpd;
elsif ((a>0 and b<0) or (a<0 and b>0)) -- result negative
and ((- abs a) < integer'low / abs b) then
-- negative overflow
int_to_bits(integer'low, temp_result);
cond_code2 <= '1';-- after Tpd;
else
int_to_bits(a * b, temp_result);
cond_code2 <= '0';-- after Tpd;
end if;
when divide =>
if b=0 then
if a>=0 then -- positive overflow
int_to_bits(integer'high, temp_result);
else
int_to_bits(integer'low, temp_result);
end if;
cond_code2 <= '1';-- after Tpd;
else
int_to_bits(a / b, temp_result);
cond_code2 <= '0';-- after Tpd;
end if;
end case;
if command /= disable then
result <= temp_result;-- after Tpd;
else
result <= X"0000_0000";-- after Tpd;
end if;
cond_code0 <= bool_to_bit(temp_result = X"00000000"); --after Tpd;
cond_code1 <= bool_to_bit(temp_result(31) = '1'); --after Tpd;
end process ALU_function;
end behaviour;
----------------------------------------------------------------
Проба теста:
use work.dp32_types.all;
use work.ALU_32_types.all;
entity alutest is
end alutest;
architecture testalu of alutest is
signal operand1,operand2: bit_vector(31 downto 0);
signal cond_code2, cond_code1, cond_code0: bit;
signal result: bit_vector(31 downto 0);
signal command: ALU_command;
component alu
port (operand1, operand2 : in bit_vector(31 downto 0);
cond_code2,cond_code1, cond_code0: out bit;
result : out bit_vector(31 downto 0);
command: in ALU_command);
end component;
begin
ALU : alu port map (operand1=>operand1, operand2=>operand2, cond_code0=>cond_code0, cond_code1=>cond_code1, cond_code2=>cond_code2,command=>command, result=>result);
end testalu;
entity alustim is
end alustim;
architecture test of alustim is
signal op1,op2: bit_vector(31 downto 0);
signal cc2, cc1, cc0: bit;
signal res: bit_vector(31 downto 0);
signal comm: ALU_comm;
component alu
port (operand1, operand2 : in bit_vector(31 downto 0);
cond_code3,cond_code1, cond_code0: out bit;
result : out bit_vector(31 downto 0);
command: in ALU_command);
end component;
begin
ALU: alu port map (op1, op2, cc0, cc1, cc2,comm, res);
op1<= X"1111_1111" after 0 ns,
X"0000_0000" after 20 ns,
X"1111_1111" after 40 ns,
X"0000_0000" after 60 ns,
X"1111_1111" after 80 ns,
X"0000_0000" after 100 ns,
X"1111_1111" after 120 ns,
X"0000_0000" after 140 ns,
X"1111_1111" after 160 ns,
X"0000_0000" after 180 ns,
X"1111_1111" after 200 ns,
X"0000_0000" after 220 ns,
X"1111_1111" after 240 ns,
X"0000_0000" after 260 ns,
X"1111_1111" after 280 ns,
X"0000_0000" after 300 ns,
X"1111_1111" after 320 ns,
X"0000_0000" after 340 ns,
X"1111_1111" after 360 ns,
X"0000_0000" after 380 ns;
op2 <= X"1111_1111" after 0 ns,
X"0000_0000" after 40 ns,
X"1111_1111" after 80 ns,
X"0000_0000" after 120 ns,
X"1111_1111" after 160 ns,
X"0000_0000" after 200 ns,
X"1111_1111" after 140 ns,
X"0000_0000" after 180 ns,
X"1111_1111" after 220 ns,
X"0000_0000" after 260 ns,
X"1111_1111" after 300 ns,
X"0000_0000" after 340 ns,
X"1111_1111" after 380 ns,
X"0000_0000" after 420 ns;
--comm <= add after 80 ns,
-- subtract after 160 ns,
-- multiply after 240 ns,
-- divide after 300 ns;
end ONE;
-----------------------------------
configuration aluconfig of alustim is
for testalu
for alu:alu use entity work.alu(test);
end for;
end for;
end aluconfig;
E-mail: 
info@telesys.ru
