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process(clk,rst)
variable rg_str : std_logic_vector(15 downto 0);
begin
if rst = '1' then
rg <= (others => '0');
elsif clk = '1' and clk'event then
str <= rg_str(0);
rg_str := ce & rg_str(15 downto 1); -- это задержка на SRL
if ce = '1' then
rg <= di;
else
rg <= '0'& rg(15 downto 1);
end if;
end if;
end process;
do <= rg(0);
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