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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;entity act_counter is
port
(
clk, reset : in std_logic;
count : out std_logic_vector (7 downto 0)
);
end act_counter;architecture behave of act_counter is
signal count_i : std_logic_vector (7 downto 0);
begin
process (clk, reset)
begin
if (reset = '0') then
count_i <= (others => '0');
elsif (clk'event) then
count_i <= count_i + '1';
end if;
end process;
count <= count_i;
end behave;
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