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A register, declared with keyword reg, represents a variable in Verilog. Where net data types do not store values, reg data types do. Registers can be assigned only in an always block, task or
function. When a variable is assigned a value in an always block that has a clock edge event expression (posedge or negedge), a flip-flop is synthesized by LeonardoSpectrum. To avoid the creation of flip-flops for reg data types, separate the combinational logic into a different always block (that does not have a clock edge event expression as a trigger).
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