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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mcnt is
port(clk : in std_logic; f : out std_logic);
end mcnt;
architecture a of mcnt is
signal cnt : std_logic_vector(3 downto 0) ;
begin
process(clk, cnt)
begin
if rising_edge(clk) then
if cnt < 8 then
cnt <= cnt + 1;
else
cnt <= (others => '0');
end if;
end if;
f <= cnt(3);
end process;
end a;
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