Отправлено UR 17 февраля 2004 г. 14:37 В ответ на: Еще ... Надо use UNISIM.VComponents.all; +правильно описать в проекте коргеновский модуль отправлено UR 17 февраля 2004 г. 14:21

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

-- *************************** --
-- *** ENTITY of Mem *** --
-- *************************** --
entity mem is
Port
(
);
end mem;

architecture Behavioral of mem is

-- ******************************** --
-- *** COMPONENTES of Mem *** --
-- ******************************** --
component fifo32x1023
port (
din : in std_logic_VECTOR(31 downto 0);
wr_en : in std_logic;
wr_clk : in std_logic;
rd_en : in std_logic;
rd_clk : in std_logic;
ainit : in std_logic;
dout : out std_logic_VECTOR(31 downto 0);
full : out std_logic;
empty : out std_logic);
end component;

-- ***************************************** --
-- *** SIGNALS and CONSTANS of Mem *** --
-- ***************************************** --
-- fifo signals --
signal f1_wr_en: std_logic;
signal f1_rd_en: std_logic;
signal f1_ainit: std_logic;
signal f1_din: std_logic_VECTOR(31 downto 0);
signal f1_dout: std_logic_VECTOR(31 downto 0);
signal f1_full: std_logic;
signal f1_empty: std_logic;

-- ******************* --
-- *** MAIN of Mem *** --
-- ******************* --
begin

-- ********************************** --
-- *** INSTANTIATION of Mem *** --
-- ********************************** --
fifo_inst : fifo32x1023
port map (
din => Pcm_vector,--f1_din,
wr_en => f1_wr_en,
wr_clk => clk_MCLK1,
rd_en => f1_rd_en,
rd_clk => clk_CLK,
ainit => f1_ainit,
dout => f1_dout,
full => f1_full,
empty => f1_empty);
end Behavioral;

• В проекте у меня так все и описано, но (+) — vladx   (17.02.2004 14:53, 219 байт)